INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Implementation of FFT Algorithm Based on Vedic Maths Using FPGA
Authors Name:
Vishal Rajeshkumar Panchal
, Prof. Milind Shah
Unique Id:
IJSDR1605052
Published In:
Volume 1 Issue 5, May-2016
Abstract:
Abstract—This Fast Fourier transform (FFT) is an efficient algorithm to compute the N point DFT. The FFT is a computationally intensive digital signal processing function, but the Implementation of FFT requires large number of complex multiplications, so to make this process rapid and simple, it is necessary for a multiplier to be fast and power efficient. To solve this problem, UrdhvaTiryagbhyam sutra in Vedic mathematics is used. It is based on a concept through which the generation of all partial products can be done and then, concurrent addition of these partial products can be done. The conventional multiplication method requires more time & area than Vedic algorithms. In this paper, the algorithm for FFT using Vedic maths is proposed.
Keywords:
FFT, Vedic Mathematics, Vedic Multiplier, UrthvaTiryagbhyam, Vertically and Crosswise Algorithm.
Cite Article:
"Implementation of FFT Algorithm Based on Vedic Maths Using FPGA", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 5, page no.265 - 269, May-2016, Available :http://www.ijsdr.org/papers/IJSDR1605052.pdf
Downloads:
000337070
Publication Details:
Published Paper ID: IJSDR1605052
Registration ID:160329
Published In: Volume 1 Issue 5, May-2016
DOI (Digital Object Identifier):
Page No: 265 - 269
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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