INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
An asynchronous circuit, or self-timed circuit, is a sequential digital logic circuit which is not having any global clock. The communication and data transfer between functional blocks is performed by indicating completion of operation and instruction, using handshaking protocol. While in synchronous design the complete working of different blocks are coordinated by clock signal. All blocks will respond only at the positive or negative edge of the clock. Most of the digital devices today are using synchronous logic design techniques. Because it is easy to design, availability of pool of tools for complete design flow, expertise in synchronous design techniques. But future Nano CMOS VLSI Technology will not be compatible with synchronous designs as physical parameters variation will be dominant. These increased timing variations will reduce robustness, reliability and performance. However asynchronous circuit designs have the potential to be faster, less power consumption, lowering electromagnetic interference, with modular designs in large systems (SoCs).
"Design of 8 bit Pipelined Adder using Xilinx ISE", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 6, page no.385 - 389, June-2016, Available :http://www.ijsdr.org/papers/IJSDR1606067.pdf
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Publication Details:
Published Paper ID: IJSDR1606067
Registration ID:160569
Published In: Volume 1 Issue 6, June-2016
DOI (Digital Object Identifier):
Page No: 385 - 389
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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