INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Implementation of an efficient full adder Using Systematic Cell Design Methodology
Authors Name:
Anila Susan George
, Jyothish Chandran G , Anu Raj
Unique Id:
IJSDR1607046
Published In:
Volume 1 Issue 7, July-2016
Abstract:
In this paper, an efficient full adder using Systematic Cell Design Methodology (SCDM) is explained. The design is first implemented for 1 bit and then extended to 4 bit also. The circuit was implemented using Mentor Graphics tools at 180 nm technology. Performance parameters like average power, average propagation delay and Power Delay Product (PDP) are compared with existing hybrid adders like FADPL and FASRCPL. The proposed adder has less number of transistors in the critical path leading to less propagation delay. The use of transmission gate throughout the design ensures high driving capability and full voltage swing at the output. The proposed adder is found to be working efficiently when compared to other adders in terms of average power, average propagation delay and PDP.
Keywords:
Systematic cell design methodology, three input XOR/XNOR,full adder, transmission gate, low power high performance
Cite Article:
"Implementation of an efficient full adder Using Systematic Cell Design Methodology ", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 7, page no.267 - 270, July-2016, Available :http://www.ijsdr.org/papers/IJSDR1607046.pdf
Downloads:
000336256
Publication Details:
Published Paper ID: IJSDR1607046
Registration ID:160637
Published In: Volume 1 Issue 7, July-2016
DOI (Digital Object Identifier):
Page No: 267 - 270
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
Facebook Twitter Instagram LinkedIn