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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016 open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15 |
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| Paper Title: | SIP CONTROLLER FOR MASTER CORE VERIFICATION USING UVM. |
| Authors Name: | Shyamala S.C , Kalpana.S , Manasa.B , Bindu.L |
| Unique Id: | IJSDR1609045 |
| Published In: | Volume 1 Issue 9, September-2016 |
| Abstract: | ABSTRACT A serial data link standard named Serial Peripheral Interface is verified using UVM. This protocol demonstrates the ability to transform incoming parallel communication from a wishbone bus, into serial communication that is being transferred using the SPI protocol. Serial Peripheral Interface (SPI) is Serial synchronous interface that facilitates the transfer of synchronous serial data in full duplex mode. SPI use for communication with peripheral devices where we want to transfer data very fast and within real time constraints. SPI master core consist of three parts Serial interface, Clock generation and Wishbone interface. The SPI core has seven 32-bit register through the wishbone compatible interface. The serial interface consists of slave select lines, serial clock lines, as well as input and output data lines. It communicates in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select line. Serial Peripheral Interface of symmetrical structure can be simulated using Questa 10.0b. It is a popular interface used for connecting peripherals to each other and to microprocessors. In This thesis an implemented code coverage which gives an idea about how much percentage of given design has been triggered with written verification plan, In this thesis functional coverage has also done which can cover every possible working functionality of SPI core design and with the use of assertion can track some of the RTL level bug in available design. In this thesis twelve number of test cases has used which covers 100% functional coverage and 100% code coverage and got two RTL level bugs which helps design engineer to improve with the design coding style. |
| Keywords: | Virtual interface, Master_agent_top, Master agent , Master_config. Master driver, Master sequencer, Master_monitor and Slave_agent_top |
| Cite Article: | "SIP CONTROLLER FOR MASTER CORE VERIFICATION USING UVM.", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 9, page no.301 - 309, September-2016, Available :http://www.ijsdr.org/papers/IJSDR1609045.pdf |
| Downloads: | 000337070 |
| Publication Details: | Published Paper ID: IJSDR1609045 Registration ID:160811 Published In: Volume 1 Issue 9, September-2016 DOI (Digital Object Identifier): Page No: 301 - 309 Publisher: IJSDR | www.ijsdr.org ISSN Number: 2455-2631 |
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