IJSDR
IJSDR
INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15

Issue: March 2024

Volume 9 | Issue 3

Impact factor: 8.15

Click Here For more Info

Imp Links for Author
Imp Links for Reviewer
Research Area
Subscribe IJSDR
Visitor Counter

Copyright Infringement Claims
Indexing Partner
Published Paper Details
Paper Title: Design of a Robust 13T SRAM Bitcell for Operation in Low Voltages
Authors Name: GOKILAPRIYA S , DR. O.SARANIYA
Unique Id: IJSDR1703014
Published In: Volume 2 Issue 3, March-2017
Abstract: Continuous transistor scaling, coupled with growing demand for low-voltage operation, near the device threshold voltage (VT) increases the susceptibility of VLSI circuits to soft errors, especially when exposed to high radiating environments. The most vulnerable of these circuits are memory arrays that are susceptible to radiation effects than circuits powered at nominal supply voltages. Soft errors like Single Event Upsets (SEUs) occur when an energetic particle hits a sensitive node in a circuit, a transient current pulse generated due to an injected charge, changes the node voltage causing a bit flip in the memory cell. Radiation hardening of such memory blocks is achieved by implementing large bitcells or using Error-Correcting Codes (ECCs). But ECC may entail significant area, performance, and power dissipation penalties. Also, ECC only detects and corrects the error at the time the faulty word is being read, not when it occurs. So, Radiation-Harden-By-Design (RHBD) techniques are targeted at memory cells. The proposed radiation-hardened 13T Static Random Access Memory (SRAM) targeted at low-voltage functionality maintains high soft-error robustness. It employs dual-driven separated-feedback mechanism to tolerate upsets with charge deposits of 500fC. The cell provides better immunity to soft errors when compared to 6T SRAM cell. A 4x4 memory macro was designed and tested using LFSR showing read and write functionality at a scaled voltage of 1V.
Keywords: critical charge, low voltage, radiation hardening, single event upset (SEU), static random access memory (SRAM), linear feedback shift register (LFSR), memory array.
Cite Article: "Design of a Robust 13T SRAM Bitcell for Operation in Low Voltages", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.2, Issue 3, page no.81 - 87, March-2017, Available :http://www.ijsdr.org/papers/IJSDR1703014.pdf
Downloads: 000336256
Publication Details: Published Paper ID: IJSDR1703014
Registration ID:170081
Published In: Volume 2 Issue 3, March-2017
DOI (Digital Object Identifier):
Page No: 81 - 87
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

Click Here to Download This Article

Article Preview

Click here for Article Preview







Major Indexing from www.ijsdr.org
Google Scholar ResearcherID Thomson Reuters Mendeley : reference manager Academia.edu
arXiv.org : cornell university library Research Gate CiteSeerX DOAJ : Directory of Open Access Journals
DRJI Index Copernicus International Scribd DocStoc

Track Paper
Important Links
Conference Proposal
ISSN
DOI (A digital object identifier)


Providing A digital object identifier by DOI
How to GET DOI and Hard Copy Related
Open Access License Policy
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License
Creative Commons License
This material is Open Knowledge
This material is Open Data
This material is Open Content
Social Media
IJSDR

Indexing Partner