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International Journal of Scientific Development and Research - IJSDR
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Paper Title: MODIFIED DESIGN OF SHA HASHING INSTRUCTIONS FOR AREA OPTIMISED RISC PROCESSOR ARCHITECTURE
Authors Name: Priynash Trivedi , Abhishek Singh
Unique Id: IJSDR1808031
Published In: Volume 3 Issue 8, August-2018
Abstract: Our approach is to propose a fast and secure scheme for digital image encryption using only two-diffusion process based on nested chaotic attractor and the Secure Hash Algorithm SHA-3 to generate a secret key. The main advantages of our chaotic sequence used are the efficiency, simplicity and rapidity, all these features are very important it can be implemented on embedded systems. Proposed work develop a new 32 bit instruction format and a new decoder based RISC instruction set for SHA-3 encryption and hashing, modified architecture can consider as Application Specific Instruction Processor (ASIP), the proposed work in developed on Vertex family course grain FPGA VERTEX-4 and Xilinx 12.2 EDA has been used for the development of the work. The design is been verified with ISE environment of Xilinx simulation.
Keywords: SHA-Secure Hash Algorithm, RISC-Reduce Instruction Set Computer, FPGA- Field Programmable Gate Array, UACI-unified averaged changed intensity
Cite Article: "MODIFIED DESIGN OF SHA HASHING INSTRUCTIONS FOR AREA OPTIMISED RISC PROCESSOR ARCHITECTURE", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.3, Issue 8, page no.194 - 199, August-2018, Available :http://www.ijsdr.org/papers/IJSDR1808031.pdf
Downloads: 0001306
Publication Details: Published Paper ID: IJSDR1808031
Registration ID:180596
Published In: Volume 3 Issue 8, August-2018
DOI (Digital Object Identifier):
Page No: 194 - 199
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

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