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International Journal of Scientific Development and Research - IJSDR
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Authors Name: Pankaj Kumar Sikdar , Shraddha Shrivastava
Unique Id: IJSDR1904039
Published In: Volume 4 Issue 4, April-2019
Abstract: With advancement of microelectronics devices and its technology scaling, the main objective of design i.e. low power consumption can be easily obtained. For any digital integrated circuit the power dissipation depends on operating voltage, number of transistors incorporated in circuit. The conventional CMOS design for three input EX-OR logic can be possible with 10 or more than 10 transistors, with the methodology discussed in this paper, the similar circuit for three inputs EX-OR logic can be implemented by sixteen transistors. The proposed design consists of transmission gate, systematic cell design methodology (SCDM) and one latch. The proposed design consumes 70% (85%) smaller PDP than that of SCDM based XO-10 (conventional LPHS-FA) EX-OR logic design with CMOS technology. This design is useful for variety of applications such as Data encryption, Arithmetic circuits, Binary to Gray encoding etc. The novel design explained in this paper is simulated at 130nm MOSFET technology.
Keywords: Adders, Transistors, Delay, CMOS integrated circuits, Logic gates, Hybrid adder, EX-OR.
Cite Article: "PROPOSED LOW PDP EXCLUSIVE-OR GATE USING 130NM FET TECHNOLOGY", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.4, Issue 4, page no.167 - 175, April-2019, Available :http://www.ijsdr.org/papers/IJSDR1904039.pdf
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Publication Details: Published Paper ID: IJSDR1904039
Registration ID:190384
Published In: Volume 4 Issue 4, April-2019
DOI (Digital Object Identifier):
Page No: 167 - 175
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

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