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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH
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ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
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Volume 9 | Issue 4

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Paper Title:	Design of a Three Bit Ternary Prefix Adder using CNFET
Authors Name:	Lijitha Merin Jacob , Prof. Ayoob Khan T. E.
Unique Id:	IJSDR1905021
Published In:	Volume 4 Issue 5, May-2019
Abstract:	Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in power consumption and propagation delay by 43% and 72% respectively.
Keywords:	CNFET, Prefix Adders, Ternary Logic, Low power
Cite Article:	"Design of a Three Bit Ternary Prefix Adder using CNFET", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.4, Issue 5, page no.127 - 132, May-2019, Available :http://www.ijsdr.org/papers/IJSDR1905021.pdf
Downloads:	000337071
Publication Details:	Published Paper ID: IJSDR1905021 Registration ID:190497 Published In: Volume 4 Issue 5, May-2019 DOI (Digital Object Identifier): Page No: 127 - 132 Publisher: IJSDR \| www.ijsdr.org ISSN Number: 2455-2631

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