INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
this paper focuses on the redesign of a PLL system using the 45nm CMOS technology (GPDK045library) in CADENCE iVertuoso iAnalog iDesign iEnvironment. The proposed PLL iarchitecture iincludes ifollowing imodules: iphase and ifrequency detector(PFD) to compare phasei(or frequency) of input ireference and phase(or frequency) of feedbacki signali and generate the idifference or an error signal, icharge ipump and loop ifilter is to convert the digital iUP and iDOWN isignals into analog control voltage, ivoltage icontrolled oscillatori is to produce ithe clock output which iis ithe multiplication iof the input reference frequency and multiplication factor(N) and frequency divider is to equal the output frequency with input frequency. All modules are integrated in order produce the 1GHz output frequency from 4MHz input frequency at 1.8V DC supply and have lock time 40µs. Output clock have period jitter 44.87ps.
Keywords:
phase locked loop, charge pump, phase and frequency detector, voltage controlled oscillator and lock time.
Cite Article:
"Design and Analysis of Phase Locked Loop", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.4, Issue 8, page no.308 - 314, August-2019, Available :http://www.ijsdr.org/papers/IJSDR1908050.pdf
Downloads:
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Publication Details:
Published Paper ID: IJSDR1908050
Registration ID:190956
Published In: Volume 4 Issue 8, August-2019
DOI (Digital Object Identifier):
Page No: 308 - 314
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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