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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016 open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15 |
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| Paper Title: | DESIGN AND PERFORMNCE ANALYSIS OF LOW DENSITY PARITY CHECK ENCODER AND DECODER |
| Authors Name: | S.DALI NAIDU , ALAJANGI.RAMAKRISHNA , A.ARUNA |
| Unique Id: | IJSDR1911028 |
| Published In: | Volume 4 Issue 11, November-2019 |
| Abstract: | This paper proposes a novel encoder architecture of low-density parity-check (LDPC) Encoder and a parallel software low-density parity-check (LDPC) decoding algorithm on graphics processing units (GPUs). We utilize the specific structure of LDPC parity matrix to parallelize row and column encoding operations. An optimized method is also proposed to control memories, which can be reused for the LDPC code with different code rates to improve the utilization of hardware resources. The proposed LDPC encoder and decoder are implemented on Xilinx FPGA. According to simulation results of Modelsim, we also verify that the proposed method has the advantages of reduced resource consumption, low power, and high accuracy. The proposed encoder and decoder can achieve throughput up to 400 Mbps. In particular, with Lena binary image as the test transmission data, we present design and implementation of a solution for LDPC decoder, dedicated application specific integrated circuit (ASIC) or field programmable gate array (FPGA) implementations are proposed in recent years in order to support high throughput despite their long deployment cycle, high design and especially fixed functionalities. On the other hand, the implementations on GPU as software solution provide flexible, scalable and less expensive solutions in shorter deployment cycle. We present some GPU-based optimizations for a major LDPC decoder algorithm to obtain high throughput in digital communication systems. Experimental results demonstrate that the proposed LDPC decoder achieves more than 1.27 Gbps peak throughput on a single GPU. |
| Keywords: | LDPC Encoder, LDPC Decoder, GPU, ASIC,FPGA |
| Cite Article: | "DESIGN AND PERFORMNCE ANALYSIS OF LOW DENSITY PARITY CHECK ENCODER AND DECODER", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.4, Issue 11, page no.166 - 170, November-2019, Available :http://www.ijsdr.org/papers/IJSDR1911028.pdf |
| Downloads: | 000337212 |
| Publication Details: | Published Paper ID: IJSDR1911028 Registration ID:191130 Published In: Volume 4 Issue 11, November-2019 DOI (Digital Object Identifier): Page No: 166 - 170 Publisher: IJSDR | www.ijsdr.org ISSN Number: 2455-2631 |
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