INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Vlsi design of advanced-features aes crypto processor for data cryptography
Authors Name:
Rashmi A
, Dr. Yogesh G S
Unique Id:
IJSDR2308086
Published In:
Volume 8 Issue 8, August-2023
Abstract:
AES is a mathematical justification of data concealment. It involves implementation on the very secure symmetric cryptography method using an FPGA (field-programmable gate array). This projected construction consists of an 8-bit stream of data and five primary components. We design two separate registration banks, Key-Register and State-Register, to hold the plain text, the keys, and intermediate data. To save space, shift-rows are added to the state register. We developed an 8-bit block that can transmit and receive 8-bit data and has four inner registers that are optimised for Mix-Columns. To make different Sub-Bytes better, we integrate and simplify them. To reduce power usage, we use clock gate technology into the architecture. For picture cryptography, this work proposes a 128-bit AES architecture.Verilog HDL is castoff create this design, and a Matlab& Modelsim 6.4 C tool are used to simulate it. The Synthesis Process tool from Xilinx measures performance.
Keywords:
AES,FPGA
Cite Article:
"Vlsi design of advanced-features aes crypto processor for data cryptography", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 8, page no.588 - 593, August-2023, Available :http://www.ijsdr.org/papers/IJSDR2308086.pdf
Downloads:
000338720
Publication Details:
Published Paper ID: IJSDR2308086
Registration ID:208230
Published In: Volume 8 Issue 8, August-2023
DOI (Digital Object Identifier):
Page No: 588 - 593
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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