Implementation of 64-bit BCD Adder using Majority Gates

Prashu Chauhan , Manoj Bandil

CMOS, QCA, Majority gates , BCD adder

As technology is growing very fast, to cope with technology, advance techniques are used for designing circuits or systems. In today’s era low power, high speed and small area are the key parameters of new technique. CMOS technology gives all the mentioned parameters in desired values, still there are some limitations. Quantum-dot cellular automata (QCA) technology provides a promising opportunity to overcome the limits of conventional CMOS technology. This paper explains the design of 64-bit BCD adder using Majority gates. Xilinx 14.5 ISE simulator is used for analysis of this BCD adder.

Published Paper   E-Certificate

"Implementation of 64-bit BCD Adder using Majority Gates", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.4, Issue 8, page no.217 - 223, August-2019, Available :https://ijsdr.org/papers/IJSDR1908034.pdf

Volume 4 Issue 8, August-2019

Pages : 217 - 223

Paper Reg. ID: IJSDR_190929

Published Paper Id: IJSDR1908034

Downloads: 000347036

Research Area: Engineering

Country: gwalior, mp, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR1908034

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR1908034

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition