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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH
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ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
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Paper Title:	FPGA Implementation of Enhanced Montgomery Modular For Fast Multiplication
Authors Name:	Akanksha Jain , Prof Rajesh Khatri , Dr PP Bansod
Unique Id:	IJSDR2306137
Published In:	Volume 8 Issue 6, June-2023
Abstract:	This Paper proposed an enhanced Montgomery and efficient implementation of Modular Multiplication. Cryptographyoprocess is usedufor providingphigh informationmsecurity when a data is transferredmfrom transmitter to receiver. Various using methods like RSA, ECC, the Digital Signature Algorithm. The propose Montgomery algorithm usin RSA algorithim of cryptography is implemented in two different input both the inputs are 8 bit input. Coding have been done in Verilog language and the results are simulated on Vivado Software. For physical testing, we have used an FPGA NESYS 4 DDR hardware board that have Artix-7 FPGA chip on it produced by digilent company. The propose method shows good results in term of the number of slice flip flop , LUTs, and number of IOBs and power consumption. The proposed method shows better results as compare to other previous methods in term of different result parameters.
Keywords:	FPGA, Montgomery, Multiplication, NESYS 4 DDR , LUTs, IOB and Slice
Cite Article:	"FPGA Implementation of Enhanced Montgomery Modular For Fast Multiplication", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 6, page no.960 - 967, June-2023, Available :http://www.ijsdr.org/papers/IJSDR2306137.pdf
Downloads:	000337351
Publication Details:	Published Paper ID: IJSDR2306137 Registration ID:207245 Published In: Volume 8 Issue 6, June-2023 DOI (Digital Object Identifier): Page No: 960 - 967 Publisher: IJSDR \| www.ijsdr.org ISSN Number: 2455-2631

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