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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016 open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15 |
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| Paper Title: | Design of AXI4 Slave Device Using VERILOG |
| Authors Name: | Harish T L , Dr. M C Chandrashekhar , Dr. Eshwarappa M N |
| Unique Id: | IJSDR2306202 |
| Published In: | Volume 8 Issue 6, June-2023 |
| Abstract: | Validating the essential components of the advanced extensible interface (AXI) is the major focus of the proposed system. It is required to examine all the five channels while validating the memory transactions of the AXI bus. These channels are the read address, read data, read response, write address, and write response. For the purpose of carrying out the verification process in this specific piece of work, a strategy that is built on Verification Intellectual Property cores (VIP) is used as the foundation. Read and write transactions from the same and distinct memory locations have been verified as part of the VIP design using the quantitative values of Busy Count, Valid Count, and its Bus Utilisation. This was done as part of the VIP design. This has been done both for the same memory location and for various memory locations. System Verilog is used to perform a simulation of the whole testing environment. It has been proven that read and write operations from the same memory locations as well as from other memory locations. The new AMBA AXI 4.0 standard would allow for burst durations of up to 32 beats, would update the criteria for write responses, would do away with locked transactions, and would contain information about the compatibility of various components. By using this protocol, it is possible to interface a total of 16 masters and 16 slaves at the same time.In addition to that, the work done on the design and implementation of an AMBA AXI4 Master Model for high performance SoCs that uses Verilog HDL coding is discussed in this paper. The simulation results are shown using a tool built by Xilinx, and the article concludes with a summary of the study's findings. |
| Keywords: | Advanced extensible interface (AXI); Verification Intellectual Property cores (VIP); Advanced Microcontroller Bus Architecture (AMBA); system-on-chip (SoC); Advanced Peripheral Bus (APB);Advanced RISC Machines(ARM); |
| Cite Article: | "Design of AXI4 Slave Device Using VERILOG", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 6, page no.1474 - 1479, June-2023, Available :http://www.ijsdr.org/papers/IJSDR2306202.pdf |
| Downloads: | 000337352 |
| Publication Details: | Published Paper ID: IJSDR2306202 Registration ID:207417 Published In: Volume 8 Issue 6, June-2023 DOI (Digital Object Identifier): Page No: 1474 - 1479 Publisher: IJSDR | www.ijsdr.org ISSN Number: 2455-2631 |
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