INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Verification of an AXI4 slave device using System Verilog
Authors Name:
Harish T L
, Dr. M C Chandrashekhar , Dr. Eshwarappa M N
Unique Id:
IJSDR2306217
Published In:
Volume 8 Issue 6, June-2023
Abstract:
Because of its accessibility, comprehensive documentation, and lack of license costs, AMBA protocols have become the de facto standard for 32-bit embedded processors. High-performance, high-frequency system topologies are now feasible thanks to the AMBA AXI 4 protocol. It is great for systems that need plenty of bandwidth and little latency, and it lets you run at high frequencies without resorting to elaborate bridges. The existing AHB and APB interfaces may be used with it, and it allows for a variety of connection topologies to be built. The Verification Environment for this project is constructed using System Verilog code. This project's goal is to verify the AMBA-based design of the AXI4 Slave Interface.
Keywords:
Advanced Microcontroller Bus Architecture (AMBA), Advanced Peripheral Bus (APB), AMBA High performance Bus (AHB), Advanced Extensible Interface (AXI).
Cite Article:
"Verification of an AXI4 slave device using System Verilog", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 6, page no.1617 - 1621, June-2023, Available :http://www.ijsdr.org/papers/IJSDR2306217.pdf
Downloads:
000337352
Publication Details:
Published Paper ID: IJSDR2306217
Registration ID:207427
Published In: Volume 8 Issue 6, June-2023
DOI (Digital Object Identifier):
Page No: 1617 - 1621
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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