Design of Modified Low Power And High Speed Carry Select Adder Using Brent Kung Adder
AMALA MARIA ALEX
, NIDHISH ANTONY
BK Adder-Brent Kung Adder,RCA-Ripple Carry Adder,CSLA-Carry Select Adder,RLBKCSLA-Regular Linear Brent Kung Carry Select Adder,MLBKCSLA-Modified Linear Brent Kung Carry Select Adder,RSQBKCSLA-Regular Square Root Brent Kung Carry Select Adder,MSQBKCSLA-Modified Square Root Brent Kung Carry Select Adder,PSQBKCSLA-Proposed Square Root Brent Kung Carry Select Adder
In order to perform the addition of two numbers adder is used. Adder also forms the integral part of ALU. Besides this application of adder in computer, it is also employed to calculate address and indices and also operation codes. Different algorithm in Digital Signal Processing such as FIR and IIR are also employed using adder. What all matter is speed and so it is the most important constraint. The important areas of VLSI areas are low power, high speed and data logic design. In Carry Select adder the possible value of input carry are 0 and 1. So in advance, the result can be calculated. Further we have the multiplexer stage, for calculating the result in its advanced stage. The conventional design is the use of dual Ripple Carry Adders (RCAs) and then there is a multiplexer stage. Here, one RCA (Cin=0) is replaced by Brent kung adder. As, RCA (for Cin=1) and Brent Kung adder (for Cin=0) consume more chip area, so an add-one scheme i.e., Binary to Excess-l converter is introduced. Also the square root adder architectures of CSA are designed using Brent Kung adder in order to reduce the power and delay of adder. In proposed model a modification is done by using D-LATCH instead of Binary to Excess-1 to improve the speed and reduce power. Here the Binary to Excess-1 Converter is replaced with a D-Latch. Initially when en=1, the output of the BK adder is fed as input to the D-Latch and the output of the D-latch follows the input and given as an input to the multiplexer. When en=0, the last state of the D input is trapped and held in the latch and therefore the output from the BK adder is directly given as an input to the Mux without any delay.
"Design of Modified Low Power And High Speed Carry Select Adder Using Brent Kung Adder", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 8, page no.196 - 204, August-2016, Available :https://ijsdr.org/papers/IJSDR1608025.pdf
Volume 1
Issue 8,
August-2016
Pages : 196 - 204
Paper Reg. ID: IJSDR_160674
Published Paper Id: IJSDR1608025
Downloads: 000347229
Research Area: Engineering
Country: KOTTAYAM, Kerala, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
