Review on Multilevel Inverter with Reduced Switches

Ms.Pratibha Patil , Prof.Dhananjay Sargar , Prof.Mohit Farad

Multilevel DC to AC inverter, PIC Microcontroller, PUC Inverter, Cascaded Inverters

Multilevel inverters have been widely accepted for high-power high-voltage applications Though the multilevel inverters hold attractive features, usage of more switches in the conventional configuration poses a limitation to its wide range application. Therefore, 7-level multilevel inverter topology is introduced using less number of switches and gate trigger circuitry, thereby ensuring the minimum switching losses, reducing size and installation cost. By providing gate trigger signal, AC output voltage is generated.

Published Paper   E-Certificate

"Review on Multilevel Inverter with Reduced Switches", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.2, Issue 12, page no.102 - 109, December-2017, Available :https://ijsdr.org/papers/IJSDR1712015.pdf

Volume 2 Issue 12, December-2017

Pages : 102 - 109

Paper Reg. ID: IJSDR_170880

Published Paper Id: IJSDR1712015

Downloads: 000347035

Research Area: Engineering

Country: Solapur, Maharashtra, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR1712015

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR1712015

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition