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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016 open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15 |
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| Paper Title: | Implementation Of Digital Clock With Stopwatch On FPGA |
| Authors Name: | L. Supriya , K. Leela Bhavani , P.V.B. Janaki , P. Devashish |
| Unique Id: | IJSDR2306229 |
| Published In: | Volume 8 Issue 6, June-2023 |
| Abstract: | The industry standard for real-time operations and linear control systems today is FPGA (Field Programmable Gate Array)-based implementation. The objective here is to build a digital clock with stopwatch using Verilog and either the FPGA i.e., Zed board. The system that will be constructed will have a 6-digit clock with hour, minute, and second hands utilizing extremely affordable equipment that will be placed in an ideal location. The design has every component that a digital clock should have, and because it is synchronous, the overall latency is minimal. The Software "Xilinx Vivado" is used to implement a Verilog HDL code that is used to design the notion mentioned above. |
| Keywords: | Control systems, FPGA, Verilog, Zed board, Synchronous, Latency, Xilinx Vivado |
| Cite Article: | "Implementation Of Digital Clock With Stopwatch On FPGA", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 6, page no.1709 - 1712, June-2023, Available :http://www.ijsdr.org/papers/IJSDR2306229.pdf |
| Downloads: | 000337351 |
| Publication Details: | Published Paper ID: IJSDR2306229 Registration ID:207406 Published In: Volume 8 Issue 6, June-2023 DOI (Digital Object Identifier): Page No: 1709 - 1712 Publisher: IJSDR | www.ijsdr.org ISSN Number: 2455-2631 |
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